//PC
module PC_mod(
	clk,
	rst,

	pc_en_i,
	s_pc_i,
	c_pc_i,

	pc_mux_i,
	pc_data_i,
	
	mem_en_o,
	mem_addr_o,
	pc_o,
	
	ins_en_o
);
input clk;
input rst;

input pc_mux_i;
input [31:0] pc_data_i;
input pc_en_i;
input [2:0] s_pc_i;
input c_pc_i;
output mem_en_o;
output [31:0] mem_addr_o;
output [31:0] pc_o;
output ins_en_o;

reg [31:0] PC;
reg mem_en_o;
reg ins_en_o;

always @ (posedge clk ) begin
	if(rst == 1'b1) begin
		PC <= 32'h3ffffffc;
		mem_en_o <= 1'b0;
		ins_en_o <= 1'b0;
	end else if (s_pc_i[0] == 1'b1) begin
		PC <= PC;
		mem_en_o <= mem_en_o;
		ins_en_o <= ins_en_o;
	end else if(pc_en_i == 1'b1) begin
		if (c_pc_i == 1'b1) begin
			PC <= 32'h40000000;
			mem_en_o <= 1'b0;
			ins_en_o <= 1'b0;
		end else begin
			if (pc_mux_i == 1'b1) begin
				PC <= pc_data_i;
			end else begin
				PC <= PC + 32'h4;
			end
			mem_en_o <= 1'b1;
			ins_en_o <= 1'b1;
		end
	end else begin
		PC <= 32'h3ffffffc;
		mem_en_o <= 1'b0;
		ins_en_o <= 1'b0;
	 end
end

assign mem_addr_o = PC;
assign pc_o = PC;

endmodule
